September 2019 - TuxCare

Webinar: Live Patching Linux Kernel Vulnerabilities in Scalable Hosting Environments

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Join our upcoming webinar to see how the three co-founders of Webslice, a managed cloud services company based in the Netherlands, provide mission-critical services to enterprises, saving 40 hours of admin per vulnerability with KernelCare and AWS. Learn more on the upcoming KernelCare and AWS webinar.

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5 Linux Events You Shouldn’t Miss at Arm TechCon 2019

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On October 8–10, at the San Jose Convention Center, the KernelCare team will be in booth #1238, discussing the importance of live kernel patching. We have been live-patching Linux kernels on ARM architectures for a while now, and we’re excited to discuss embedded systems, the internet of things, and other hot-button topics.

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KernelCare now works with vulnerability scanners

Screen Shot 2019-09-20 at 11.47.33 PMVulnerability scanners are programs that scan your system to tell you whether you have software installed with known vulnerabilities. However, sometimes these scanners can give false positives. After too many false positives, analysts will begin to ignore reports, as reviewing a false positive takes time and money, and incident response and threat hunting are affected. The impact of false positives can be severe when benign reports create exhaustive overhead for your analysts. Continue reading “KernelCare now works with vulnerability scanners”

Four Things To Do When in San Jose for Arm TechCon 2019

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On October 8–10, 2019, KernelCare will be attending Arm TechCon 2019  at the San Jose Convention Center. KernelCare have been live-patching Linux kernels on ARM architectures for a while now, and we’re keen to keep spreading the word amongst the experts of the ARM world. We’ll be at booth #1238; you can book a meeting with KernelCare’s CEO, Igor Seletskiy, here.

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What is an Advanced RISC Machine?

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Electrical engineering is a field packed with acronyms. “Advanced RISC Machine” is an older name for the modern-day ARM processor, which represents the leading form of RISC architecture. “RISC” stands for reduced instruction set computer, and refers to a type of microprocessor architecture that optimizes performance by limiting the number of cycles per instruction within its CPU programs. 

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Resources

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